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features description applications TPS62410 slvs737 ? february 2007 2.25mhz 2x800ma dual step down converter in small 3x3mm qfn package high efficiency?up to 95% the TPS62410 device is a synchronous dual step-down dc-dc converter optimized for battery v in range from 2.5 v to 6 v powered portable applications. it provides two 2.25 mhz fixed frequency operation independent output voltage rails powered by 1-cell output current 2 x 800ma li-ion or 3-cell nimh/nicd batteries. the device is adjustable output voltage from 0.6 v to v in also suitable to operate from a standard 3.3v or 5v voltage rail. easyscale? optional one pin serial interface for dynamic output voltage adjustment with an input voltage range of 2.5v to 6v, the TPS62410 is ideal to power portable applications like power save mode at light load currents smart phones, pdas, and other portable equipment. 180 out of phase operation with the easyscale? serial interface the output output voltage accuracy in pwm mode 1% voltages can be modified during operation. it typical 32 m a quiescent current for both therefore supports dynamic voltage scaling for low converters power dsp and processors. 100% duty cycle for lowest dropout the TPS62410 operates at 2.25mhz fixed switching available in a 10-pin qfn (3 3mm) frequency and enter the power save mode operation at light load currents to maintain high efficiency over the entire load current range. for low noise applications the devices can be forced into fixed cell phones, smart-phones frequency pwm mode by pulling the mode/data pdas, pocket pcs pin high. in the shutdown mode, the current omap? and low power dsp supply consumption is reduced to 1.2 m a. the device allows portable media players the use of small inductors and capacitors to achieve digital radio a small solution size. digital cameras the TPS62410 is available in a 10-pin leadless package (3 3mm qfn) please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. easyscale, omap, powerpad are trademarks of texas instruments. production data information is current as of publication date. copyright ? 2007, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. www.ti.com v out2 sw1 fb1 sw2 adj2 def_1 out2 c in 10 f vin2.5v C 6v vin en_1en_2 mode/ data TPS62410 gnd upto800ma r21 360k r22 180k =1.8v l2 2.2 h c =22 f c ff2 33pf upto800ma r11 270k r12 180k v out1 =1.5v l1 2.2 h c out1 =22 f v = 5 v in v = 3.6 v in power save mode mode/data = 0 forced pwm mode mode/data = 1 0 10 20 30 40 50 60 70 80 90 100 efficiency - % 0.01 0.1 1 10 100 1000 i - ma out v = 3.3 v out v = 3.6 v in v = 5 v in
absolute maximum ratings dissipation ratings recommended operating conditions TPS62410 slvs737 ? february 2007 ordering information (1) t a part default output output qfn (1) ordering package number voltage (2) current package marking (1) out1 800ma ?40 c to 85 c TPS62410 adjustable drc TPS62410drc cat out2 800ma (1) for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti web site at www.ti.com . over operating free-air temperature range (unless otherwise noted) (1) value unit input voltage range on v in (2) ?0.3 to 7 v voltage range on en, mode/data, def_1 ?0.3 to v in +0.3, 7 v maximum current into mode/data 500 m a voltage on sw1, sw2 ?0.3 to 7 v voltage on adj2, fb1 ?0.3 to v in +0.3, 7 v esd rating (3) hbm human body nodel 2 kv charge device model 1 kv machine model 200 v t j(max) maximum junction temperature 150 c t a operating ambient temperature range ?40 to 85 c t stg storage temperature range ?65 to 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. exposure to absolute?maximum?rated conditions for extended periods may affect device reliability. (2) all voltage values are with respect to network ground terminal. (3) the human body model is a 100pf capacitor discharged through a 1.5k w resistor into each pin. the machine model is a 200pf capacitor discharged directly into each pin. package r q ja power rating for t a 25 c derating factor above t a = 25 c drc 49 c/w 2050mw 21mw/ c over operating free-air temperature range (unless otherwise noted) min nom max unit vin supply voltage 2.5 6 v output voltage range for adjustable voltage 0.6 vin v t a operating ambient temperature -40 85 c t j operating junction temperature -40 125 c 2 submit documentation feedback www.ti.com
electrical characteristics TPS62410 slvs737 ? february 2007 v in = 3.6v, v out = 1.8v, en = v in , mode = gnd, l = 2.2 m h, c out = 20 m f, t a = ?40 c to 85 c typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit supply current v in input voltage range 2.5 6.0 v one converter, i out = 0ma. pfm mode enabled 19 29 m a (mode = 0) device not switching, en1 = 1 or en2 = 1 two converter, i out = 0ma. pfm mode enabled 32 48 m a (mode = 0) device not switching, i q operating quiescent current en1 = 1 and en2 = 1 i out = 0ma, mode/data = gnd, for one 23 m a converter, v out 1.575v (1) i out = 0ma, mode/data = v in , for one 3.6 ma converter, v out 1.575v (1) en1, en2 = gnd, v in = 3.6v (2) 1.2 3 i sd shutdown current m a en1, en2 = gnd, v in ramped from 0v to 3.6v (3) 0.1 1 falling 1.5 2.35 v uvlo undervoltage lockout threshold v rising 2.4 enable en1, en2 v ih high-level input voltage, en1, en2 1.2 v in v v il low-level input voltage, en1, en2 0 0.4 v i in input bias current, en1, en2 en1, en2 = gnd or vin 0.05 1.0 m a def_1 input i in input biasd current def_1 def_1 = gnd or vin 0.01 1.0 m a mode/data v ih high-level input voltage, 1.2 v in v mode/data v il low-level input voltage, 0 0.4 v mode/data i in input bias current, mode/data mode/data = gnd or vin 0.01 1.0 m a v oh acknowledge output voltage high open drain, via external pullup resistor v in v v ol acknowledge output voltage low open drain, sink current 500 m a 0 0.4 v interface timing t start start time 2 m s t h_lb high time low bit, logic 0 detection signal level on mode/data pin is > 1.2v 2 200 m s t l_lb low time low bit, logic 0 detection signal level on mode/data pin < 0.4v 2x 400 m s t h_lb t l_hb low time high bit, logic 1 detection signal level on mode/data pin < 0.4v 2 200 m s t h_lb high time high bit, logic 1 detection signal level on mode/data pin is > 1.2v 2x 400 m s t l_hs t eos end of stream t eos 2 m s t ackn duration of acknowledge condition v in 2.5v to 6v 400 520 m s (mode/date line pulled low by the device) t valack acknowledge valid time 2 m s t timeout timeout for entering power save mode/data pin changes from high to low 520 m s mode (1) device is switching with no load on the output, l = 3.3 m h, value includes losses of the coil (2) these values are valid after the device has been already enabled one time (en1 or en2 = high) and supply voltage v in has not powered down. (3) these values are valid when the device is disabled (en1 and en2 low) and supply voltage v in is powered up. the values remain valid until the device has been enabled first time (en1 or en2 = high). after first enable, note 3 becomes valid. 3 submit documentation feedback www.ti.com
TPS62410 slvs737 ? february 2007 electrical characteristics (continued) v in = 3.6v, v out = 1.8v, en = v in , mode = gnd, l = 2.2 m h, c out = 20 m f, t a = ?40 c to 85 c typical values are at t a = 25 c (unless otherwise noted) parameter test conditions min typ max unit power switch r ds(on) p-channel mosfet on-resistance, v in = v gs = 3.6v 280 620 m w converter 1,2 i lk_pmos p-channel leakage current v ds = 6.0v 1 m a r ds(on) n-channel mosfet on-resistance v in = v gs = 3.6v 200 450 m w converter 1,2 i lk_sw1/sw2 leakage current into sw1/sw2 pin includes n-chanel leakage currnet, 6 7.5 m a v in = open, v sw = 6.0v, en = gnd (4) i limf forward current out 1/2 800ma 2.5v v in 6.0v 1.0 1.2 1.38 a limit pmos and nmos t sd thermal shutdown increasing junction temperature 150 c thermal shudown hysteresis decreasing junction temperature 20 c oscillator fsw oscillator frequency 2.5v vin 6.0v 2.0 2.25 2.5 mhz output v out adjustable output votage range 0.6 v in v v ref reference voltage 600 mv voltage positioning active, mode/data = gnd, 1.01x v out (pfm) device operating in pfm mode, vin = 2.5v to ?1.5% 2.5% v out 5.0v (6) (7) dc output voltage accuracy pfm mode, adjustable and fixed output mode/data = gnd; device operating in pwm ?1% 0% 1% voltage (5) mode vin = 2.5v to 6.0v (7) v out v in = 2.5v to 6.0v, mode/data = v in , fixed pwm ?1% 0% 1% operation, 0ma < i out < i outmax (8) dc output voltage load regulation pwm operation mode 0.5 %/a t start up start-up time activation time to start switching (9) 170 m s t ramp v out ramp up time time to ramp from 5% to 95% of v out 750 m s (4) at pins sw1 and sw2 an internal resistor of 1m w is connected to gnd (5) output voltage specification does not include tolerance of external voltage programming resistors (6) configuration l typ 2.2 m h, c out typ 20 m f, see parameter measurement information, the output voltage ripple depends on the effective capacitance of the output capacitor, larger output capacitors lead to tighter output voltage tolerance (7) in power save mode, pwm operation is typically entered at i psm = v in /32 w . (8) for v out > 2.2v, v in min = v out +0.3v (9) this time is valid if one converter turns from shutdown mode (en2 = 0) to active mode (en2 =1) and the other converter is already enabled (e.g., en1 = 1). in case both converters are turned from shutdown mode (en1 and en2 = low) to active mode (en1 and/or en2=1) a value of typ 80 m s for ramp up of internal circuits needs to be added. after t start the converter starts switching and ramps v out . 4 submit documentation feedback www.ti.com
device information pin assignments TPS62410 slvs737 ? february 2007 terminal functions terminal i/o description no. name (qfn) adj2 1 i input to adjust output voltage of converter 2. in adjustable version (TPS62410) connect a external resistor divider between vout2, this pin and gnd to set output voltage between 0.6v and vin. if easyscale? interface is used for converter 2, this pin must be directly connected to the output. mode/data 2 i this pin has 2 functions: 1. operation mode selection: with low level, power save mode is enabled where the device operates in pfm mode at light loads and enters automatically pwm mode at heavy loads. pulling this pin to high forces the device to operate in pwm mode over the whole load range. 2. easyscale? interface function: one wire serial interface to change the output voltage of both converters. the pin has an open drain output to provide an acknowledge condition if requested. the current into the open drain output stage may not exceed 500 m a. the interface is active if either en1 or en2 is high. vin 3 i supply voltage, connect to vbat, 2.5v to 6v fb1 4 i direct feedback voltage sense input of converter 1, connect directly to vout 1. an internal feed forward capacitor is connected between this pin and the error amplifier. in case of fixed output voltage versions or when the interface is used, this pin is connected to an internal resistor divider network. def_1 5 i/o this pin defines the output voltage of converter 1. the pin acts in TPS62410 as an analog input for output voltage setting via external resistors. in fixed default output voltage versions this pin is a digital input to select between two fixed default output voltages. in TPS62410 an external resistor network needs to be connected to this pin to adjust the default output voltage. sw1 6 switch pin of converter1. connected to inductor 1 en1 7 i enable input for converter1, active high gnd 8 i gnd for both converters, this pin should be connected with the powerpad en2 9 i/o enable input for converter 2, active high sw2 10 switch pin of converter 2. connected to inductor 2 powerpad? connect to gnd 5 submit documentation feedback www.ti.com def_1 fb1 mode/data vin en1 sw2 adj2 gnd en2 po w e r pad sw1 1 23 4 5 10 9 87 6 top view drc package
functional block diagram TPS62410 slvs737 ? february 2007 a. in fixed output voltage version, the pin def_1 is connected to an internal digital input and disconnected from the error amplifier b. to set the output voltage of converter 2 via easyscale interface, adj2 pin must be directly connected to vout2 6 submit documentation feedback www.ti.com internalcompensated error amp. sawtoothgenerator skip comp. low pwmcomp. average current detector skip mode entry vref controlstage gate driver pmos currentlimit comparator nmos currentlimit comparator load comparator vref- 1% fbvout1 fb_vout undervoltage lockout thermalshutdown softstart vin gnd mode error amp. sawtoothgenerator pwmcomp. vref controlstage gate driver pmos currentlimit comparator nmos currentlimit comparator load comparator fb_vout2 thermalshutdown softstart vin gnd mode clk 180 easy scale interface clk 0 clk 180 2.25mhz oscillator converter 1 converter 2 sw1sw2 adj2 fb1 def1 mode/ data en1 en2 vin gnd ext. res. network reference average current detector skip mode entry ackmosfet open drain internalcompensated skip comp. vref +1% fb_vout skip comp. low vref- 1% fb_vout skip comp. vref +1% fb_vout note a ri3 ri 1 ri..n int. resistornetwork c ff 25pf register def1_high def1_low ri 1 ri..n int. resistornetwork c ff 25pf register def2 note b
parameter measurement information typical characteristics table of graphs TPS62410 slvs737 ? february 2007 figure no. efficiency v out1 = 1.2v 1 efficiency v out1 = 1.5v 2 efficiency v out2 = 1.8v 3 efficiency v out2 = 3.3v 4 efficiency vs v in 5, 6 dc output accuracy v out1 = 1.5v 7 dc output accuracy v out2 = 3.3v 8 f osc vs v in 9 i q for one converter 10 i q for both converters, not switching 11 r dson pmos vs v in 12 r dson nmos vs v in 13 light load output voltage ripple in power save mode 14 output voltage ripple in forced pwm mode 15 output voltage ripple in pwm mode 16 forced pwm/ pfm modetransition 17 load transient response pfm/pwm 18 load transient response pwm operation 19 line rransient response 20 startup timing one converter 21 typical operation v in = 3.6v, v out1 = 1.575v, vout2 = 1.8v 22 typical operation v in = 3.6v, v out1 = 1.8v, v out2 = 3.0v 23 typical operation v in = 3.6v, v out1 = 1.2v, v out2 = 1.2v 24 dynamic voltage positioning 25 7 submit documentation feedback www.ti.com sw1 fb 1 sw2 adj2 def_1 vin en_1en_2 mode/ data TPS62410 gnd r11 r12 l1 vin 2.5 v - 6 v c 10 f in m 2.2 h lps4018 m v out1 c 2x10 f grm21br61a106k out1 m r21r22 l2 v out2 c 2x10 f grm21br61a106k out2 m c33 pf ff2 2.2 h lps4018 m
TPS62410 slvs737 ? february 2007 typical characteristics (continued) figure no. soft start 26 easyscale protocol overview 27 easyscale protocol without acknowledge 28 easyscale protocol including acknowledge 29 easyscale ? bit coding 30 mode/data pin: mode selection 31 mode/data pin: power save mode / interface communication 32 typical application circuit 1.5v / 2.85v adjustable outputs 33,34 layout diagram 35 pcb layout 36 efficiency v out = 1.2v efficiency v out = 1.5v figure 1. figure 2. efficiency v out2 = 1.8v efficiency v out2 = 3.3v figure 3. figure 4. 8 submit documentation feedback v = 5 v in v = 3.6 v in power save mode mode/data = 0 forced pwm mode mode/data = 1 0 10 20 30 40 50 60 70 80 90 100 efficiency - % 0.01 0.1 1 10 100 1000 i - ma out v = 3.3 v out v = 3.6 v in v = 5 v in www.ti.com 0 10 20 30 40 50 60 70 80 90 100 efficiency - % 0.01 0.1 1 10 100 1000 i - ma out v = 1.8 v out v = 2.7 v in v = 5 v in v = 3.6 v in v = 2.7 v in v = 5 v in v = 3.6 v in power save mode mode/data = 0 forced pwm mode mode/data = 1 0 10 20 30 40 50 60 70 80 90 100 efficiency - % 0.01 0.1 1 10 100 1000 i - ma out mode/data = low v = 5 v v = 3.7 v v = 3.3 v v = 2.7 v in in in in mode/data = high v = 5 v v = 3.7 v v = 3.3 v v = 2.7 v in in in in v = 1.5 v out 0 10 20 30 40 50 60 70 80 90 100 0.01 0.1 1 10 100 1000 i - ma out efficiency - % v = 1.2 v out mode/data = low v = 5 v v = 3.7 v v = 3.3 v v = 2.7 v in in in in mode/data = high v = 5 v v = 3.7 v v = 3.3 v v = 2.7 v in in in in
TPS62410 slvs737 ? february 2007 efficiency vs v in , v out = 1.575v efficiency vs v in , v out = 3.3v figure 5. figure 6. dc output accuracy v out1 = 1.5v dc output accuracy v out2 = 3.3v figure 7. figure 8. 9 submit documentation feedback www.ti.com 1.425 1.450 1.475 1.500 1.525 1.550 1.575 v dc - v o ut mode/data = low, pfm mode, voltage positioning active mode/data = high, forced pwm mode v = 1.5 v out 0.01 0.1 1 10 100 1000 i - ma out v = 2.7 v in v = 5 v in v = 3.7 v in v = 5 v in v = 3.7 v in v = 3.3 v in v = 2.7 v in v = 3.3 v in 3.200 3.250 3.300 3.350 3.400 v dc - v out 0.01 0.1 1 10 100 1000 i - ma out mode/data = low, pfm mode, voltage positioning active mode/data = high, forced pwm mode v = 5 v in v = 5 v in v = 3.3 v out v 3.7 v in = v 4.2 v in = pwm mode operation v = 3.7 v in v = 4.2 v in 50 55 60 65 70 75 80 85 90 95 100 2 3 4 5 6 efficiency mode/data = 0 v = 1.575 v out i = 10 ma out i = 1 ma out i = 200 ma out v - v in 50 60 70 80 90 100 3 4 5 6 v - v in efficiency mode/data = 0 v = 3.3 v out i = 100 ma out i = 10 ma out i = 1 ma out
TPS62410 slvs737 ? february 2007 f osc vs v in i q for one converter, not switching figure 9. figure 10. i q for both converters, not switching r dson pmos vs v in figure 11. figure 12. 10 submit documentation feedback www.ti.com 2 2.05 2.1 2.15 2.2 2.25 2.3 2.35 2.4 2.45 2.5 2.5 3 3.5 4 4.5 5 5.5 6 v - v in fosc - mhz -40 c 85 c 25 c 17 18 19 20 21 22 23 24 2.5 3 3.5 4 4.5 5 5.5 6 v - v in iddq - a m -40c 85c 25c 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 2.5 3 3.5 4 4.5 5 5.5 6 v - v in rdson - w 85c 25c -40c 28 30 32 34 36 38 40 42 2.5 3 3.5 4 4.5 5 5.5 6 v - v in iddq - a m 85c 25c -40c
TPS62410 slvs737 ? february 2007 light load output voltage ripple r dson nmos vs v in in power save mode figure 13. figure 14. output voltage ripple output voltage ripple in forced pwm mode in pwm mode figure 15. figure 16. 11 submit documentation feedback www.ti.com 0.05 0.1 0.15 0.2 0.25 0.3 2.5 3 3.5 4 4.5 5 5.5 6 v - v in rdson - w 85c 25c -40c iout = 10ma vout = 1.8v 20mv/div inductor current 100ma/div power save modemode/data = low time base - 10 s/div m iout = 10ma vout = 1.8v 20mv/div inductor current 100ma/div mode/data = high,forced pwm mode operation time base - 400 ns/div vout = 1.8v iout = 400ma vout ripple 20mv/div inductor current 200ma/div pwm mode operation time base - 200 ns/div
TPS62410 slvs737 ? february 2007 forced pwm/pfm mode transition load transient response pfm/pwm figure 17. figure 18. load transient response pwm operation line transient response figure 19. figure 20. 12 submit documentation feedback www.ti.com vout = 1.8v iout = 20ma vout 20mv/div entering pfm mode voltage positioning active forced pwmmode mode/data 1v/div enable power save mode time base - 20 s/div m iout= 60ma iout1 = 540ma vout = 1.575v 50mv/div voltage positioning in pfm mode reduces voltage drop during load step iout 200ma/div mode/data = low pwm mode operation time base - 100 s/div m iout= 60ma iout1 = 540ma vout = 1.575v 50mv/div iout 200ma/div mode/data = high pwm mode operation time base - 100 s/div m vin 1v/div vout 1.575 iout 200ma vin 3.6v to 4.6v vout 50mv/div mode/data = high time base - 400 s/div m
detailed description operation TPS62410 slvs737 ? february 2007 typical operation v in = 3.6v, startup timing one converter v out1 = 1.575v, v out2 = 1.8v figure 21. figure 22. typical operation v in = 3.6v, typical operation v in = 3.6v, v out1 = 1.8v, v out2 = 3.0v v out1 = 1.2v, v out2 = 1.2v figure 23. figure 24. v out1 change with easyscale the TPS62410 includes two synchronous step-down converters. the converters operate with typically 2.25mhz fixed frequency pulse width modulation (pwm) at moderate to heavy load currents. if power save mode is enabled, the converters automatically enter power save mode at light load currents and operate in pfm (pulse 13 submit documentation feedback www.ti.com sw1 5v/div sw2 5v/div i coil1 200ma/div i coil2 200ma/div v in 3.6v, v out1 : 1.575v v out2 : 1.8v i out1 = i out2 = 200ma time base - 100 ns/div vin = 3.8viout1 max = 400ma sw1 1v/div en1 / en2 5v/div vout1500mv/div icoil 500ma/div time base - 200 s/div m sw1 5v/div sw2 5v/div i coil1 200ma/div i coil2 200ma/div v in 3.6v, v out1 : 1.8v v out2 : 3.0v i out1 = i out2 = 200ma time base - 100 ns/div sw1 5v/divsw2 5v/div i coil1 200ma/div i coil2 200ma/div v in 3.6v, v out1 : 1.2v v out2 : 1.2v i out1 = i out2 = 200ma time base - 100 ns/div
converter 1 converter 2 power save mode (1) (2) TPS62410 slvs737 ? february 2007 detailed description (continued) frequency modulation). during pwm operation the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. at the beginning of each clock cycle initiated by the clock signal, the p-channel mosfet switch is turned on and the inductor current ramps up until the comparator trips and the control logic turns off the switch. each converter integrates two current limits, one in the p-channel mosfet and another one in the n-channel mosfet. when the current in the p-channel mosfet reaches its current limit, the p-channel mosfet is turned off and the n-channel mosfet is turned on. if the current in the n-channel mosfet is above the n-mos current limit threshold, the n-channel mosfet remains on until the current drops below its current limit. the two dc-dc converters operate synchronized to each other. a 180 phase shift between converter 1 and converter 2 decreases the input rms current. in the adjustable output voltage version TPS62410 the converter 1 output voltage can be set via an external resistor network on pin def_1, which operates as an analog input. in this case, the output voltage can be set in the range of 0.6v to vin v. the fb1 pin must be directly connected to the converter 1 output voltage vout1. it feeds back the output voltage directly to the regulation loop. the output voltage of converter 1 can also be changed by the easyscale serial interface. this makes the device very flexible for output voltage adjustment. in this case, the device uses an internal resistor network. in the adjustable output voltage version TPS62410, the converter 2 output voltage is set by an external resistor divider connected to adj2 pin and uses an external feed forward capacitor of 33pf. it is also possible to change the output voltage of converter 2 via the easyscale interface. in this case, the adj2 pin must be directly connected to converter 2 output voltage vout2. at TPS62410 no external resistor network may be connected. the power save mode is enabled with mode/data pin set to 0 for both converters. if the load current of a converter decreases, this converter will enter power save mode operation automatically. the transition to power save mode of a converter is independent from the operating condition of the other converter. during power save mode the converter operates with reduced switching frequency in pfm mode and with a minimum quiescent current to maintain high efficiency. the converter will position the output voltage in pfm mode to typically 1.01xvout. this voltage positioning feature minimizes voltage drops caused by a sudden load step. in order to optimize the converter efficiency at light load the average inductor current is monitored. the device changes from pwm mode to power save mode, if in pwm mode the inductor current falls below a certain threshold. the typical output current threshold depends on vin and can be calculated according to equation 1 for each converter. equation 1 : average output current threshold to enter pfm mode equation 2 : average output current threshold to leave pfm mode in order to keep the output voltage ripple in power save mode low, the output voltage is monitored with a single threshold comparator (skip comparator). as the output voltage falls below the skip comparator threshold (skip comp) of 1.01 x voutnominal, the corresponding converter starts switching for a minimum time period of typically 1 m s and provides current to the load and the output capacitor. therefore the output voltage increases and the device maintains switching until the output voltage trips the skip comparator threshold (skip comp) again. at this moment all switching activity is stopped and the quiescent current is reduced to minimum. the load is supplied by the output capacitor until the output voltage has dropped below the threshold again. 14 submit documentation feedback www.ti.com i out_pfm_enter vin dcdc 32 i out_pfm_leave vin dcdc 24
dynamic voltage positioning soft start TPS62410 slvs737 ? february 2007 detailed description (continued) hereupon the device starts switching again. the power save mode is exited and pwm mode entered in case the output current exceeds the current iout_pfm_leave, or if the output voltage falls below a second comparator threshold, called skip comparator low (skip comp low) threshold. this skip comparator low threshold is set to ?2% below nominal vout, and enables a fast transition from power save mode to pwm mode during a load step. in power save mode the quiescent current is reduced typically to 19 m a for one converter and 32 m a for both converters active. this single skip comparator threshold method in power save mode results in a very low output voltage ripple. the ripple depends on the comparator delay and the size of the output capacitor. increasing output capacitor values minimizes the output ripple. the power save mode can be disabled through the mode/data pin set to high. both converters then operate in fixed pwm mode. power save mode enable/disable applies to both converters. this feature reduces the voltage under/overshoots at load steps from light to heavy load and vice versa. it is activated in power save mode operation. it provides more headroom for both the voltage drop at a load step, and the voltage increase at a load throw-off. this improves load transient behavior. at light loads, in which the converter operate in pfm mode, the output voltage is regulated typically 1% higher than the nominal value. in case of a load transient from light load to heavy load, the output voltage drops until it reaches the skip comparator low threshold set to ?2% below the nominal value and enters pwm mode. during a load throw off from heavy load to light load, the voltage overshoot is also minimized due to active regulation turning on the n-channel switch. figure 25. dynamic voltage positioning the two converters have an internal soft start circuit that limits the inrush current during start-up. during soft start, the output voltage ramp up is controlled as shown in figure 26 . figure 26. soft start 15 submit documentation feedback www.ti.com v out_nom +1% pwm modemedium/heavy load pfm modelight load smoothincreased load pwm modemedium/heavy load pfm modelight load fast load transient pwm modemedium/heavy load comp_low threshold C1% 95%5% t ramp t startup en v out
100% duty cycle low dropout operation (3) under-voltage lockout mode selection enable TPS62410 slvs737 ? february 2007 detailed description (continued) the converters offer a low input to output voltage difference while still maintaining operation with the use of the 100% duty cycle mode. in this mode the p-channel switch is constantly turned on. this is particularly useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole battery voltage range; i.e., the minimum input voltage to maintain regulation depends on the load current and output voltage, and can be calculated as: with: iout max = maximum output current plus inductor ripple current rdson max = maximum p-channel switch rdson r l = dc resistance of the inductor vout max = nominal output voltage plus maximum output voltage tolerance with decreasing load current, the device automatically switches into pulse skipping operation in which the power stage operates intermittently based on load demand. by running cycles periodically the switching losses are minimized and the device runs with a minimum quiescent current maintaining high efficiency. the under voltage lockout circuit prevents the device from malfunctioning at low input voltages and from excessive discharge of the battery and disables the converters. the under-voltage lockout threshold is typically 1.5v, max 2.35v. in case the default register values are overwritten by the interface, the new values in the registers reg_def_1_low and reg_def_2 remain valid as long the supply voltage does not fall under the under-voltage lockout threshold, independent of whether the converters are disabled. the mode/data pin allows mode selection between forced pwm mode and power save mode for both converters. furthermore, this pin is a multipurpose pin and provides (besides mode selection) a one-pin interface to receive serial data from a host to set the output voltage. this is described in the section easyscale interface. connecting this pin to gnd enables the automatic pwm and power save mode operation. the converters operate in fixed-frequency pwm mode at moderate to heavy loads and in the pfm mode during light loads, maintaining high efficiency over a wide load current range. pulling the mode/data pin high forces both converters to operate constantly in the pwm mode even at light load currents. the advantage is the converters operate with a fixed frequency that allows simple filtering of the switching frequency for noise sensitive applications. in this mode, the efficiency is lower compared to the power save mode during light loads. for additional flexibility it is possible to switch from power save mode to forced pwm mode during operation. this allows efficient power management by adjusting the operation of the converter to the specific system requirements. in case the operation mode will be changed from forced pwm mode (mode/data = high) to power save mode enable (mode/data = 0) the power save mode will be enabled after a delay time of typically t timeout , which is a maximum of 520 m s. the forced pwm mode operation is enabled immediately with pin mode/data set to 1. the device has for each converter a separate en pin to start up each converter independently. if en1, en2 are set to high, the corresponding converter starts up with soft start as previously described. pulling en1 and en2 pin low forces the device into shutdown, with a shutdown quiescent current of typically 1.2 m a. in this mode, the p and n-channel mosfets are turned-off and the entire internal control circuitry is switched-off. for proper operation the en1 and en2 pins must be terminated and must not be left floating. 16 submit documentation feedback www.ti.com vin min vout max iout max rdson max r l
def_1 pin function 180 out of phase operation short-circuit protection thermal shutdown easyscale?: one pin serial interface for dynamic output voltage adjustment general protocol addressable registers TPS62410 slvs737 ? february 2007 detailed description (continued) the def_1 pin is dedicated to converter 1 and works as an analog input for adjustable output voltage setting. connecting an external resistor network to this pin adjusts the default output voltage to any value starting from 0.6v to v in . in pwm mode the converters operate with a 180 turn-on phase shift of the pmos (high side) transistors. it prevents the high side switches of both converters to be turned on simultaneously, and therefore smooths the input current. this feature reduces the surge current drawn from the supply. both outputs are short-circuit protected with maximum output current = i limf (p-mos and n-mos). once the pmos switch reaches its current limit, it will be turned off and the nmos turned on. the pmos only turns on again, once the current in the nmos decreases below the nmos current limit. as soon as the junction temperature, t j , exceeds typically 150 c the device goes into thermal shutdown. in this mode, the p and n-channel mosfets are turned-off. the device continues its operation when the junction temperature falls below the thermal shutdown hysteresis again. easyscale is a simple but very flexible one pin interface to configure the output voltage of both dc/dc converters. the interface is based on a master ? slave structure, where the master is typically a m controller or application processor. figure 27 and table 2 give an overview of the protocol. the protocol consists of a device specific address byte and a data byte. the device specific address byte is fixed to 4e hex. the data byte consists of five bit for information, two address bits and the rfa bit. rfa bit set to high indicates the request for acknowledge condition. the acknowledge condition is only applied if the protocol was received correctly. the advantage of easyscale compared to other one-pin interfaces is that its bit detection is, to a large extent, independent from the bit transmission rate. it can automatically detect bit rates between 1.7kbit/sec and up to 160kbit/sec. furthermore, the interface is shared with the mode/data pin and requires therefore no additional pin. all bits are transmitted msb first and lsb last. figure 28 shows the protocol without acknowledge request (bit rfa = 0), figure 29 with acknowledge (bit rfa = 1) request. prior to both bytes, device address byte and data byte, a start condition needs to be applied. for this, the mode/data pin needs to be pulled high for at least t start before the bit transmission starts with the falling edge. in case the mode/data line was already at high level (forced pwm mode selection) no start condition need be applied prior the device address byte. the transmission of each byte needs to be closed with an end of stream condition for at least t eos . in TPS62410 two registers with a data content of 5 bits can be addressed to change the output voltage of both converters. with 5 bit data content, 32 different values for each register are available. table 1 shows the addressable registers if def_1 pin acts as analog input with external resistors connected. the available output voltages for converter 1 are shown in table 3 , for converter 2 in table 4 . to generate these output voltages, a precise internal resistor divider network is used, which makes external resistors unnecessary and results therefore in an higher output voltage accuracy and less board space. 17 submit documentation feedback www.ti.com
bit decoding acknowledge mode selection TPS62410 slvs737 ? february 2007 detailed description (continued) the interface is activated if at least one of the converters is enabled (en1 or en2 is high). after the startup-time t start (170 m s) the interface is ready for data reception. table 1. addressable registers for adjustable output voltage devices register description a1 a0 d4 d3 d2 d1 d0 reg_def_1_high not available in TPS62410 adjustable version 0 1 reg_def_1_low converter 1 output voltage setting 0 0 TPS62410 see table 3 reg_def_2 converter 2 output voltage 1 0 TPS62410 see table 4 , connect adj2 pin directly to vout 2 don?t use 1 1 the bit detection is based on a pwm scheme, where the criterion is the relation between t low and t high . it can be simplified to: high bit: t high > t low , but with t high at least 2x t low , see figure 30 low bit: tlow> thigh, but with tlow at least 2x thigh, see figure 30 the bit detection starts with a falling edge on the moded/data pin and ends with the next falling edge. depending on the relation between t low and t high a 0 or 1 is detected. the acknowledge condition is only applied if: acknowledge is requested by a set rfa bit the transmitted device address matches with the device address of the device 16 bits were received correctly in this case, the device turns on the internal ackn-mosfet and pulls the mode/data pin low for the time tackn, which is max. 520 m s. the acknowledge condition is valid after an internal delay time t valack . this means the internal ackn-mosfet is turned on after t valack , when the last falling edge of the protocol was detected. the master controller keeps the line low during this time. the master device can detect the acknowledge condition with it?s input by releasing the mode/data pin after tvalack and read back a 0. in case of an invalid device address or not correctly received protocol, no acknowledge condition will be applied, thus the internal mosfet will not be turned on and the external pullup resistor pulls mode/data pin high after t valack . the mode/data pin can be used again after the acknowledge condition ends. note: the acknowledge condition may only be requested in case the master device has an open drain output. in case of a push pull output stage it is recommended to use a series resistor in the mode/data line to limit the current to 500 m a in case of an accidentally requested acknowledge to protect the internal ackn-mosfet. because of the mode/data pin is used for two functions, interface and a mode selection, the device needs to determine when it has to decode the bit stream or to change the operation mode. the device enters forced pwm mode operation immediately whenever the mode/data pin turns to high level. the device stays also in forced pwm mode during the whole time of a protocol reception. with a falling edge on the mode/data pin the device starts bit decoding. if the mode/data pin stays low for at least t timeout , the device get?s an internal timeout and power save mode operation is enabled. 18 submit documentation feedback www.ti.com
TPS62410 slvs737 ? february 2007 a protocol which is sent within this time will be ignored, because the falling edge for the mode change will be first interpreted as start of the first bit. in this case it is recommended to send first the protocol and change at the end of the protocol to power save mode. figure 27. easy scale protocol overview table 2. easy scale bit description byte bit name transmission description number direction device 7 da7 in 0 msb device address address 6 da6 in 1 byte 5 da5 in 0 4 da4 in 0 4ehex 3 da3 in 1 2 da2 in 1 1 da1 in 1 0 da0 in 0 lsb device address databyte 7(msb) rfa in request for acknowledge, if high, acknowledge condition will applied by the device 6 a1 address bit 1 5 a0 address bit 0 4 d4 data bit 4 3 d3 data bit 3 2 d2 data bit 2 1 d1 data bit 1 0(lsb) d0 data bit 0 ack out acknowledge condition active 0, this condition will only be applied in case rfa bit is set. open drain output, line needs to be pulled high by the host with a pullup resistor. this feature can only be used if the master has an open drain output stage. in case of a push pull output stage acknowledge condition may not be requested! figure 28. easy scale protocol without acknowledge 19 submit documentation feedback www.ti.com data in start data out ack rfa a1 a0 d4 d3 d2 d1 d0 da7 0 da6 1 da5 0 da4 0 da3 1 da2 1 da1 1 da0 0 device address databyte eos start eos start da7 0 t start mode, statichigh or low mode, statichigh or low data in t start t eos t eos da0 0 rfa 0 d0 1 address byte data byte
TPS62410 slvs737 ? february 2007 figure 29. easy scale protocol including acknowledge figure 30. easyscale ? bit coding figure 31. mode/data pin: mode selection figure 32. mode/data pin: power save mode/interface communication 20 submit documentation feedback www.ti.com power save mode forced pwm mode power save mode t timeout mode/data t start t start t eos t eos address byte data byte forced pwm mode power save mode t timeout mode/data power save mode low bit (logic 0) high bit (logic 1) t low t high t low t high mode, statichigh or low t ackn acknowledgetrue , data line pulled down bydevice data in data out acknowledgefalse , no pull down controller needs topullup data line via a resistor to detect ackn ackn da7 0 mode, statichigh or low t eos t valack da0 0 rfa 1 d0 1 t start t start address byte data byte
TPS62410 slvs737 ? february 2007 table 3. selectable output voltages for converter 1, with def1 pin as analog input (TPS62410) TPS62410 output voltage [v] d4 d3 d2 d1 d0 register reg_def_1_low 0 v out1 adjustable output with resistor network on def_1 pin 0 0 0 0 0 0.6v with def_1 pin connected to v out1 1 0.825 0 0 0 0 1 2 0.85 0 0 0 1 0 3 0.875 0 0 0 1 1 4 0.9 0 0 1 0 0 5 0.925 0 0 1 0 1 6 0.95 0 0 1 1 0 7 0.975 0 0 1 1 1 8 1.0 0 1 0 0 0 9 1.025 0 1 0 0 1 10 1.050 0 1 0 1 0 11 1.075 0 1 0 1 1 12 1.1 0 1 1 0 0 13 1.125 0 1 1 0 1 14 1.150 0 1 1 1 0 15 1.175 0 1 1 1 1 16 1.2 1 0 0 0 0 17 1.225 1 0 0 0 1 18 1.25 1 0 0 1 0 19 1.275 1 0 0 1 1 20 1.3 1 0 1 0 0 21 1.325 1 0 1 0 1 22 1.350 1 0 1 1 0 23 1.375 1 0 1 1 1 24 1.4 1 1 0 0 0 25 1.425 1 1 0 0 1 26 1.450 1 1 0 1 0 27 1.475 1 1 0 1 1 28 1.5 1 1 1 0 0 29 1.525 1 1 1 0 1 30 1.55 1 1 1 1 0 31 1.575 1 1 1 1 1 21 submit documentation feedback www.ti.com
TPS62410 slvs737 ? february 2007 table 4. selectable output voltages for converter 2, (adj2 connected to v out ) output voltage [v] d4 d3 d2 d1 d0 for register reg_def_2 0 v out2 adjustable output with resistor network on adj2 0 0 0 0 0 0.6v with adj2 pin connected to v out2 1 0.85 0 0 0 0 1 2 0.9 0 0 0 1 0 3 0.95 0 0 0 1 1 4 1.0 0 0 1 0 0 5 1.05 0 0 1 0 1 6 1.1 0 0 1 1 0 7 1.15 0 0 1 1 1 8 1.2 0 1 0 0 0 9 1.25 0 1 0 0 1 10 1.3 0 1 0 1 0 11 1.35 0 1 0 1 1 12 1.4 0 1 1 0 0 13 1.45 0 1 1 0 1 14 1.5 0 1 1 1 0 15 1.55 0 1 1 1 1 16 1.6 1 0 0 0 0 17 1.7 1 0 0 0 1 18 1.8 1 0 0 1 0 19 1.85 1 0 0 1 1 20 2.0 1 0 1 0 0 21 2.1 1 0 1 0 1 22 2.2 1 0 1 1 0 23 2.3 1 0 1 1 1 24 2.4 1 1 0 0 0 25 2.5 1 1 0 0 1 26 2.6 1 1 0 1 0 27 2.7 1 1 0 1 1 28 2.8 1 1 1 0 0 29 2.85 1 1 1 0 1 30 3.0 1 1 1 1 0 31 3.3 1 1 1 1 1 22 submit documentation feedback www.ti.com
application information output voltage setting converter1 adjustable default output voltage setting (4) converter 2 (5) TPS62410 slvs737 ? february 2007 the output voltage can be calculated to: to keep the operating current to a minimum, it is recommended to select r 12 within a range of 180k w to 360k w . the sum of r 12 and r 11 should not exceed ~1m w . for higher output voltages than 3.3v, it is recommended to choose lower values than 180k w for r12. route the def_1 line away from noise sources, such as the inductor or the sw1 line. the fb1 line needs to be directly connected to the output capacitor. an internal feed forward capacitor is connected to this pin, therefore there is no need for an external feed forward capacitor for converter 1. the default output voltage of converter 2 can be set by an external resistor network. for converter 2 the same recommendations apply as for converter 1. in addition to that, a 33pf external feed forward capacitor c ff2 for good load transient response must be used. the output voltage can be calculated to: route the adj2 line away from noise sources, such as the inductor or the sw2 line. in case the interface is used for converter 2, connect adj2 pin directly to v out2 figure 33. typical application circuit 1.5v/2.85v adjustable outputs, low pfm voltage ripple optimized 23 submit documentation feedback www.ti.com sw1 fb 1 sw2 adj2 def_1 vin 3.3 v C 6 v vin en_1en_2 mode/ data TPS62410 gnd l1 c 10 f in m 2.2 h m r11 270 k w r12180 k w v = 1.5 v up to 800 ma out1 c = 22 f out1 m v = 2.85 v up to 800 ma out2 l2 c ff2 33 pf 3.3 h m r21825 k w r22220 k w c = 22 f out2 m v out v ref 1 r 11 r 12 with an internal reference voltage v ref typical 0.6v v out v ref 1 r 21 r 22 with an internal reference voltage v ref typical 0.6v
output filter design (inductor and output capacitor) inductor selection (6) (7) TPS62410 slvs737 ? february 2007 application information (continued) figure 34. typical application circuit 1.5v/2.85v adjustable outputs the device is optimized to operate with inductors of 2.2 m h to 4.7 m h and output capacitors of 10 m f to 22 m f. for operation with a 2.2 m h inductor, a 22 m f capacitor is suggested. the selected inductor has to be rated for its dc resistance and saturation current. the dc resistance of the inductance will influence directly the efficiency of the converter. therefore an inductor with lowest dc resistance should be selected for highest efficiency. equation 6 calculates the maximum inductor current under static load conditions. the saturation current of the inductor should be rated higher than the maximum inductor current as calculated with equation 7 . this is recommended because during heavy load transient the inductor current will rise above the calculated value. with: f = switching frequency (2.25mhz typical) l = inductor value d i l = peak to peak inductor ripple current i lmax = maximum inductor current the highest inductor current will occur at maximum vin. open core inductors have a soft saturation characteristic and they can usually handle higher inductor currents versus a comparable shielded inductor. a more conservative approach is to select the inductor current rating just for the maximum switch current of the corresponding converter. it must be considered, that the core material from inductor to inductor differs and will have an impact on the efficiency especially at high switching frequencies. 24 submit documentation feedback www.ti.com sw1 fb 1 sw2 adj2 def_1 vin 3.3 v C 6 v vin en_1en_2 mode/ data TPS62410 gnd l1 c 10 f in m 2.2 h m r11 270 k w r12180 k w v = 1.5 v up to 800 ma out1 c = 10 f out1 m v = 2.85 v up to 800 ma out2 l2 c ff2 33 pf 3.3 h m r21825 k w r22220 k w c = 10 f out2 m i l vout 1 vout vin l ? i lmax i outmax i l 2
output capacitor selection (8) (9) input capacitor selection layout considerations TPS62410 slvs737 ? february 2007 application information (continued) refer to table 5 and the typical applications for possible inductors. table 5. list of inductors dimensions [mm 3 ] inductor type supplier 2.8x2.6 1.4 vlf3014 tdk 3 3 1.4 lps3015 coilcraft 3.9 3.9 1.7 lps4018 coilcraft the advanced fast response voltage mode control scheme of the two converters allows the use of small ceramic capacitors with a typical value of 10 m f, without having large output voltage under and overshoots during heavy load transients. ceramic x7r/x5r capacitors having low esr values result in lowest output voltage ripple and are therefore recommended. if ceramic output capacitors are used, the capacitor rms ripple current rating will always meet the application requirements. the rms ripple current is calculated as: at nominal load current the inductive converters operate in pwm mode and the overall output voltage ripple is the sum of the voltage spike caused by the output capacitor esr plus the voltage ripple caused by charging and discharging the output capacitor: where the highest output voltage ripple occurs at the highest input voltage vin. at light load currents the converters operate in power save mode and the output voltage ripple is dependent on the output capacitor value. the output voltage ripple is set by the internal comparator delay and the external capacitor. higher output capacitors like 22 m f values minimize the voltage ripple in pfm mode and tighten dc output accuracy in pfm mode. because of the nature of the buck converter having a pulsating input current, a low esr input capacitor is required for best input voltage filtering and minimizing the interference with other circuits caused by high input voltage spikes. the converters need a ceramic input capacitor of 10 m f. the input capacitor can be increased without any limit for better input voltage filtering. as for all switching power supplies, the layout is an important step in the design. proper function of the device demands careful attention to pcb layout. care must be taken in board layout to get the specified performance. if the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well as emi problems. it is critical to provide a low inductance, impedance ground path. therefore, use wide and short traces for the main current paths as indicated in bold in figure 35 . the input capacitor should be placed as close as possible to the ic pins as well as the inductor and output capacitor. 25 submit documentation feedback www.ti.com vout vout 1 vout vin l ? 1 8 cout ? esr i rmscout vout 1 vout vin l ? 1 2 3
TPS62410 slvs737 ? february 2007 connect the gnd pin of the device to the powerpad of the pcb and use this pad as a star point. for each converter use a common power gnd node and a different node for the signal gnd to minimize the effects of ground noise. connect these ground nodes together to the powerpad (star point) underneath the ic. keep the common path to the gnd pin, which returns the small signal components and the high current of the output capacitors as short as possible to avoid ground noise. the output voltage sense lines (fb 1, adj2, def_1) should be connected right to the output capacitor and routed away from noisy components and traces (e.g., sw line). if the easyscale interface is operated with high transmission rates, the mode/data trace must be routed away from the adj2 line to avoid capacitive coupling into the adj2 pin. a gnd guard ring between the mode/data pin and adj2 pin avoids potential noise coupling. figure 35. layout diagram 26 submit documentation feedback www.ti.com sw1 fb 1 def_1 vin 2.5 v C 6 v vin en_1en_2 mode/ data TPS62410 gnd r11 r12 powerpad r21r22 sw2adj2 c 10 f in m c out2 c 33 pf ff2 l1 3.3 h m 3.3 h m c out2 l2
TPS62410 slvs737 ? february 2007 figure 36. pcb layout 27 submit documentation feedback www.ti.com c in c out1 c out2 gnd pinconnected with power pad
tape and reel information package materials information www.ti.com 17-may-2007 pack materials-page 1
device package pins site reel diameter (mm) reel width (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant TPS62410drcr drc 10 mla 330 12 3.3 3.3 1.1 8 12 pkgorn t2tr-ms p TPS62410drct drc 10 mla 180 12 3.3 3.3 1.1 8 12 pkgorn t2tr-ms p tape and reel box information device package pins site length (mm) width (mm) height (mm) TPS62410drcr drc 10 mla 346.0 346.0 29.0 TPS62410drct drc 10 mla 190.0 212.7 31.75 package materials information www.ti.com 17-may-2007 pack materials-page 2
package materials information www.ti.com 17-may-2007 pack materials-page 3

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